Process for the intermediate amplification of digital signals and intermediate amplifiers for digital signals

ABSTRACT

An intermediate amplification process for digital signals with pulse regeneration, determines the phase difference between the receiving timing signal and the local transmission timing signal and alters the phase of the local transmission timing signal as a function of the phase difference. It is particularly advantageous that the receiving timing signal is used as the transmission timing signal as soon as the phase difference becomes essentially zero. It is possible in this manner to minimize both the startup time delay and the packet spacing, as the number of bits to be stored intermediately may be kept low.

BACKGROUND

1. Field of the Invention

The invention concerns a process for intermediate amplification ofdigital signals, with amplitude and pulse regeneration, wherein thepulse regeneration comprises the following process steps: derivation ofa receiving pulse signal from a received signal, reading the bits of thesignal received with the receiving pulse signal into a buffer memory andreading out the bits with a local transmission pulse signal. Theinvention further concerns an intermediate amplifier for digitalsignals, with an amplitude and a pulse regeneration circuit. The pulseregeneration circuit includes a receiving pulse signal derivationcircuit, a buffer memory, a control circuit and a local transmissionpulse signal generator. A T7200 Multi Port Repeater Unit Controller ofthe AT&T company as described in its data sheet is an intermediateamplifier. The T7200 intermediate amplifier is intended for CSMA/CD(Carrier Sense Multiple Access/Collision Detection) access processaccording to the IEEE Standard 802.3 and satisfies the requirementsrelative to this process and standard. The CSMA/CD process is used inparticular in connnection with computer networks.

2. Description of the Related Technology

FIG. 1 shows the fundamental configuration of a CSMA/CD computer networkschematically. Computers T₁ are connected with each other bytransmission channels, so-called K₁ segments. An intermediate amplifierR₁ also referred to as a repeater, is located between each of theindividual segments. The repeater regenerates the digital signalstransmitted through the transmission channels K₁ relative to both theiramplitude and their transmission pulse. The amplitude regeneration isnecessary as the digital data signals are weakened during theirtransmission in the transmission channels.

It will become apparent in the following from FIG. 2, why pulseregeneration is required. FIG. 2a reproduces the transmitter pulsesignal, while FIG. 2b shows the transmitter data signal at the inlet ofa transmission channel K₁. At the inlet of a transmission signal K₁ andat the outlet of a repeater R₁, the transmitter data are in a fixed timerelationship with the transmitter pulse signal. In the course of thetransmission of a data signal through a transmission channel K₁, thiscorrect, fixed time reference of the data signal to the transmissionpulse signal is lost. The reasons for this are the limited transmissionband width of the transmission channels K₁, interference signals, timevariable decision thresholds of the inlet circuits of the repeaters R₁,etc.

By means of a so-called NRZ (nonreturn to zero) signal this process isshown in FIG. 2c, wherein the amplitude regeneration has already takenplace. Also, the phase shift caused by the running time of the datasignal in the transmission channel K₁ between the data at the inlet andthe outlet of a transmission channel K₁, is neglected. Due to the lossof the correct time relationship between the transmitter pulse signaland the data signal, the shaded area shown in FIG. 2c with an undefinedphase, is obtained. This phase trembling, also referred to as jitter,changes the spectral properties of the data signal and must be minimizedin order to allow pulse derivation free to errors in the receiver andthus a correct, error-free interpretation of the data signal in thereceiver circuit. The pulse regeneration in the repeater R₁ has thefunction to retransmit the data signal without jitter.

In the following, the properties and parameters of the CSMA/CDtransmission process according to the IEEE standard 802.3 are described,which are valid for the repeaters R₁ and which the repeaters R₁ are tosatisfy.

One of the properties of the CSMA/CD access process is that thetransmitted data are divided into individual packets. the packets aremade up of a preamble, segment and useful data.

The preamble includes a regular data pattern without information, whichallows the receivers, i.e., the participants or computers T₁ and therepeaters, to synchronize them on a data packet received. The minimumlength of the preamble is specified and according to the IEEE standard802.3 is 56 bits.

The control information and useful data part contains controlinformation and the useful data themselves. The minimum and maximumlengths of said control and useful data parts are also specified andamount in this process to 512 bits as the minimum length and 12 144 bitsas the maximum length.

Furthermore, the minimum time spacing in which the data packets may betransmitted is also specified. This spacing, which is also designated asthe packet spacing or inter frame gap (IFG), may be 96 us. The minimumtime spacing makes it possible for the participants and the computers T₁to prepare themselves following the completion of a data packet for thereception of the next one.

The maximum running time of a data packet between the two farthestremoved participants or computers T₁ is also specified in the network.In the case of the network discussed here, this maximum running timeamounts to 25.6 us. At a given propagation velocity of the signals inthe transmission channels K₁ the maximum spatial extent of the networkwith a known running time lag and known number of repeaters isspecified. In the case of the CSMA/CD access process according to theaforementioned standard, this maximum spatial extension amounts to 5 km.

A further parameter of said access process according to the standardcited is the bit rate which amounts to 1×10⁷ bits/s and is allowed amaximum deviation of ±0.01%. The so-called Manchester code is used forcoding, which in addition to the useful data also contains supplementalpulse information, thereby making possible secure pulse derivation bythe computers T₁ and the repeaters, independently of the data content.

From the aforementioned properties, i.e., the structure of the datapacket, the minimum time spacing between data packets and the maximumrunning time of a data packet in the network, the following requirementsare derived relative to the pulse regeneration of a repeater R₁ in aCSMA/CD network according to the IEEE Standard 802.3.

1. If the length of the preamble during the passage of a data packetthrough a repeater were shortened, it would indicate that when severalsuccessive repeaters are used the preamble would be successivelyshortened further, until finally the synchronization of a participantsor another repeater on the data packet would no longer be possible.Therefore, there exists the requirement that the length of the preamblein the course of the passage of a data packet through a repeater not beshortened, while a possible extension of the preamble is permissible.

2. If the time spacing between two successive data packets wereshortened below a certain minimum value by the use of repeaters, thiswould signify that the packet spacing in the cascading of severalrepeaters would be progressively reduced, which in turn would limit thenumber of repeaters to be inserted in succession. There are no standardsat the present time specifying minimum spacing at the receiver. However,there are draft standards specifying a minimum spacing of about 5 us. Inthe use of repeaters in the networks it must therefore be required thatthe time spacing between two successive data packets through a repeaterbe not shortened, or shortened by a certain amount only.

3. A further requirement relative to a repeater is that the start-uplag, also referred to as a start-up-delay should be as small aspossible, as explained in more detail hereinbelow. The start up delay isthe time elapsing between the receipt of the first preamble bit of adata packet and the retransmission of the data packet amplitude and/orpulse regenerated. The start up delay increases the running time of adata packet within the network, thereby reducing its maximum spatialextent; or in other words, a given spatial extent of a network limitsthe number of cascadable repeaters.

FIG. 3 shows the fundatmental structure of a conventional circuit layoutfor pulse regeneration in a repeater.

The receiving data signal is applied to the inlet 31 of the pulseregeneration circuit; it arrives at a pulse derivation and decodingstage 32. The pulse derivation and decoding stage 32 derives a receivingpulse signal from the receiving data signal, which in case of a networkis Manchester coded according to the IEEE Standard 802.3 and converts itinto the NRZ format. The NRZ data signal arrives through a line 33 atthe inlet of a buffer memory 34. The receiving pulse signal passesthrough a line 35 as a read-in pulse signal to the read-in pulse signalinlet of the buffer memory 34.

The pulse signal derivation from the receiving data signal is carriedout in the pulse derivation and decoding stage 32 usually by means of, aphase control circuit, also referred to as a Phase Lock Loop (PLL),whereby a local oscillator is synchronized with the preamble of thereceiving data signal. Following the completion of the synchronizationprocess a so-called RX carrier signal is generated, which arrivesthrough the line 36 at a control circuit 37.

Through a line 38 a readout release signal arrives at a coder 39, whichprovides for the buffer memory 34 a transmission pulse signal as thereadout pulse signal through the line 40, so that correspondingly theNRZ coded data is read out through the line 41 from the buffer memory 34and converted in the coder 39 into Manchester coded data, so that at theoutlet 42 a transmission data signal is present. As the data of thetransmission data signal are in a fixed time relationship with thereadout and transmission pulse signal, the transmission data signal isfree to phase jitters.

The control circuit 37 transmits over the line 43 a read-in releasesignal to the buffer memory 34. Over a line 44, the control circuit 37receives a so-called DOR signal, which indicates when the buffer memory34 is completely read out. A transmission pulse generator 45 producesthe transmission pulse signal for both the control circuit 37 and thecoder 39.

The buffer memory 34 is preferably realized in keeping with the FIFO(first in, first out) principle and allows an independent, synchronousin- and out reading of data. The read-in of the receiving data signalsappearing in the line 33 into the buffer 34 takes place synchronouslywith the receiving pulse signal standing at the line 35. The data areread out from the buffer memory 34 synchronously with the readout pulsesignal in the line 40, which is identical with the local transmissionpulse signal. The transmission pulse signal is asynchronous relative tothe receiving pulse signal.

The number of bits to be stored intermediately in the buffer memory 34depends on the frequency difference between the transmission andreceiving pulse signal and the maximum length of the data packet. Thiscondition is numberically visualized by the specifications of IEEEStandard 802.3.

According to the CSMA/CD process in keeping with said standard, the bitrate amounts to 1×10⁷ bits/s with a maximum deviation of ±0.01%, i.e.±1×10³ bits/s. Without the preamble, the maximum packet length is 12 144bit/s.

With a minimum bit rate, the packet duration has a minimum length ofL2+1.214279 ms.

The difference between L1 and L2 thus amounts to 242 ns. As at a bitrate of 1×10⁷ bit/s the bit time is 100 ns, this time difference of 242ns corresponds approximately to 2.5 bit times. This signifies that atleast 3 bits must be stored intermediately. If read-in takes place atthe minimum permissible bit rate and the readout at the maximumpermissible bit rate, i.e. the readout is faster than the read-in, thebuffer memory must contain prior to the readout at least 3 bits, inorder to insure that upon each readout pulse at least one bit is presentin the buffer memory.

If, on the other hand, the read in is at the maximum bit rate andreadout at the minimum bit rate, three additional bits must be storedintermediately. The minimum buffer memory capacity, also referred to asthe minimum depth of the buffer memory, must therefore amount to atleast 6 bits.

The figures determined here represent theoretical minimum values,wherein it is assumed in particular that the bit rates are within thetolerance limits specified. In the case of commercially insertedrepeaters usually more than 3 bits are stored intermediately in order toreduce the sensitivity to fluctuations of bit rates, thereby increasingoperating security.

The number of intermediately stored bits essentially determines thestatic running time of a pulse generating circuit. The static runningtime is the time between reception and retransmission of the same bit bya repeater. The concept of the static running time should not beconfused with the aforementioned start up delay, which is defined as thetime between the reception of the first preamble bit of a data packetand the retransmission of the first preamble bit of the amplitude andpulse regenerated data packet.

If n bits are stored intermediately and the transmission and receivingpulses are in agreement, the static running time is equal to or largerthan n bit times.

The control circuit 37 controls the buffer memory 34 and the coder 39over the line 43 and 38, respectively.

If the aforementioned synchronizing process in the pulse derivation anddecoding stage 32 is completed and the receiving data signal and thereceiving pulse signal are available at the outlet of said stage 32,this fact is communicated over the line 36 by means of the R_(x) carriersignal to the control circuit 37, which depending on it releases theread in into the buffer memeory over the line 43. If an adequate numberof data are stored in the buffer so that in the case of maximallydifferent read in and readout velocities always at least one bit isavailable for the readout process, the readout is released by the coder39.

At the end of a data packet, which is indicated to the control circuit37 by the R_(x) data signal, the control circuit 37 blocks the readingin of additional bits into the buffer memory 34. If the buffer 34 isthen completely read out, which is indicated to the control circuit 37over the line 44 by the DOR signal, the control circuit 37 blocks thereadout of the buffer 34 by the coder 39 over the line 38. Thetransmission of a data packet is thereby completed.

The functional group of the pulse derivation and decoding stage 32 andthe coder 39 may be an Advanced Micro Devices Company (AMD) AM7992B anddescribed in the corresponding data sheets of the company. The controlunit for such a repeater is marketed by the AT&T Microelectronics Co. inthe form of the electronic module T7200 Multi-Port Repeater UnitController and is described in the corresponding data sheet. With thismodule at least 7 bits are stored intermediately. An example for abuffer memory 34 is the electronic module 74HCT40105 of the Valvo Co.,which again is described in a data sheet of the company.

The transmission pulse generator 45 and its oscillator must satisfyrelative to its frequency accuracy the requirements of the standardselected.

With respect to FIG. 4, in the following the variations of the datapacket during its passing through the conventional pulse signalregeneration circuit shown in FIG. 3 is explained.

FIG. 4a shows the spatial distribution of a data packet at a time t=to,wherein it is assumed hypothetically that said data packet has passedthrough the repeater unaffected. In FIG. 4b the data packet altered bythe repeater is shown.

The data packet always includes control information and a useful datapart 48a and 48b, and the preamble 49a and 49b. The startup delay 50 isthe sum to the time loss generated by the synchronizing process in thepulse derivation and decoding stage 32, and the static running time 51.The time loss caused by the synchronizing process amounts for example inthe case of the electronic module AM7992B to at least four bit times.The combination of this module AM7992B with a repeater of 7 bitscorresponding to the aforementioned module T7200 of AT&T would result ina startup time delay of 50 of about 1.1 us. In a computer networkaccording to IEEE 802.3, in which the maximum running time of a datapacket between the two participants T₁ farthest removed in the networkamounts of 25.6 us, in case of a successive insertion of 25.6/1.1=23repeaters the permissible extent of the network would therefore bereduced to 0, wherein the additional running time delays caused byindividual circuit components (part of the pulse derivation and decodingstage 32), buffer memory 34 and coder 39, are neglected.

As explained above, preamble bit losses 52 occur. Due to thesynchronizing process in the pulse signal derivation, some bits of thepreamble are consumed, for example, at least 4 bits in the case of theAM7992B module. With a preamble length of 56 bits the data bits wouldhave no preamble after passing through 14 repeaters.

As the startup time delay 50 is larger than the static running time 51,the time spacing of two successive data packets increases with eachrepeater.

The discussion presented in the foregoing clearly indicates that withthe circuit shown in FIG. 3 the aforedescribed requirement relative to arepeater that the length of the preamble must not be reduced and thatthe startup time delay should be as short as possible, cannot besatisfied. The use of the circuit layout shown in FIG. 3 is possible ina network according to IEEE 802.3 to a very limited extent only.

FIG. 5 displays schematically a known extended pulse regenerationcircuit. The circuit components in FIG. 5, which correspond to those inFIG. 3, are provided with the same reference symbols and are notexplained again.

The circuit layout according to FIG. 5 differs from that of FIG. 3 inthat additionally a carrier recognition stage 55 and a stage 56 toproduce a synthetic preamble, referred to hereafter as a preamblegenerator, are provided. The inlet of the carrier recognition stage 55is connected by a line 60 to the inlet 31 of the pulse regenerationcircuit, so that the carrier recognition stage 55 is able to detect theonset of a preamble of an incoming data packet. This information isconducted to the control circuit 37 over the data line 57 with thesignal "data present". By a line 58 the control circuit 57 is connectedto a preamble generator 56, the outlet signal arrives over the line 59at the coder 39. The preamble generator 56 further receives the readoutpulse signal on the line 40 which also constitutes the transmissionpulse signal.

The carrier recognition stage 55 has a configuration such that the timedelay between the onset of the preamble appearing at its inlet and thereport to the control circuit 37 is very small, preferably shorter thanone bit time. The control circuit 37 there is informed even prior to thecompletion of the synchronizing process in the pulse derivation anddecoding stage 32 of the arrival of a data packet at the pulseregeneration circuit.

The structure of the preamble at the beginning of a data packet isunambiguously determined. It is therefore possible to transmit asynthetic preamble in place of the preamble received. The preamblegenerator 56 performs this task and produces a synthetic preamble.

When the control circuit 37 is informed by the carrier recognition stage55 of the reception of data packet, it activates following a selectivewaiting period the preamble generator 56 over the line 58 and the coder39 over the line 38. If the waiting period is chosen to be small orpractically zero, the synthetic preamble has already been sent out priorto the completion of the synchronization for the pulse derivation andbefore the buffer memeory 34 has stored an adequate number of bits. Thissignifies that the startup time delay may be very small.

If since the onset of the appearance of an incoming data packet issufficiently long period of time has passed to fill upon the memory 34,the preamble generator 56 is deactivated and the memory 34 released.Consequently, in place of the synthetic preamble from this point in timeon the preamble received is transmitted.

The further progress to the end of the data packet now corresponds tothe pulse generation circuit shown in FIG. 3 and therefore is notexplained further.

FIG. 6, shows the schematic spatial configuration of data packets. Thechanges applied to a data packet during its passage through a pulsegeneration circuit according to FIG. 5 are explained below.

FIG. 6a shows the spatial distribution of the unaffected data packet ata time t=to with the hypothetical assumption that the data packet haspassed through the repeater without alterations. In FIG. 6b, the datapacket altered by the pulse regeneration circuit shown in FIG. 5 isreproduced. The parts of the data packet, preambles and durations, tothe extent that they correspond to those in FIG. 4, are provided withthe same symbols and are not discussed further.

From a comparison of the unaffected data packet and the one altered bythe pulse generation circuit, the following may be derived:

As the carrier recognition stage 55 immediately detects the onset of anincoming data packet, a synthetic preamble part 61 may be transmitted,which is followed by the transmission of the preamble part 62 received,when the synchronizing process in the pulse generation and decodingstage 32 is completed.

It follows that compared to the data packet altered by the circuit inFIG. 3, according to the FIG. 4b the startup time delay, i.e., theperiod of time between the reception of the first preamble bit and thefirst re-transmission bit of a data packet is small. Another advantageof the pulse regeneration circuit according to FIG. 5 relative to thatof FIG. 3 is that the preamble is not shortened. A further consequenceis that the packet spacing or inter frame gap is reduced by thedifference between the startup time delay and the static running time.

SUMMARY OF THE INVENTION

In view of the above described properties of the data packet altered inkeeping with the pulse regeneration circuit of FIG. 5, the requirementsposed relative to a repeater of minimum time spacing or an unchangedinter frame gap, and a minimum running time of a data packet--asdescribed above--cannot be satisfied simultaneously. In case of a shortstartup time delay the inter frame gap is reduced strongly and slightlyonly with a large gap. In the cases of a pulse generation circuit to beused in actual practice, for this reason a compromise is reached betweenthe two requirements. With the module T7200 the waiting period betweenthe onset of the data reception and the transmission of the syntheticpreamble i.e., the startup time delay, corresponds to the static runningtime, which is determined by the number of buffered bits. Here, theinter frame gap is altered slightly only. However, with an intermediatestorage of 7 bits and an assumed signal velocity of 20 cm/ns the maximumnetwork extent is reduced by a CSMA/CD network by about 140 m perrepeater.

It is an object of the invention to provide a process for intermediateamplification of digital signals and to create a repeater, whereby it ispossible to better satisfy the requirements of intermediateamplification of a digital data signal and relative to repeaters and inparticular to minimize the startup time delay and the shortening of thepacket spacing or the inter frame gap with a slight technical effort.

Based on the aforementioned process for intermediate amplification ofdigital signals the above defined object is attained by determining thephase difference between the receiving pulse signal and the localtransmission pulse signal and modifying the phase difference.

The characteristics according to the invention make it possible tomaintain the number of bits to be stored intermediately considerablylower than in the case of conventional processes and repeaters. As shownhereinbelow it is possible on the basis of the measures andcharacteristics of the invention to eliminate the restriction of themaximum packet length, which according to the CSMA/CD access process inkeeping with IEEE 802.33 amounts to 144 bits, so that when using theintermediate storage process and the repeater of the invention it ispossible in principle to reliably process packets of arbitrary length ina network.

Another important advantage of the present invention is that thefrequency of the receiving pulse may be far outside of the toleranceband, for example, outside a tolerance band of ±1 kHz according to IEEE802.3, without affecting the safe operation of the circuit layout. Withthe process and repeater of the invention the number of bits to bestored intermediately depends only on the configuration of the memory.In contrast to the conventional memories, in which at least 7 bits mustbe stored intermediately, the repeater according to the invention iscapable of operating with a storage of a maximum of 2 bits.

According to a preferred embodiment of the invention, the phase of thelocal transmission is altered so that the receiving pulse signal and thetransmission pulse signal are in essential agreement.

An alternative embodiment of the invention uses the receiving pulsesignal as the transmission pulse signal, wherein the phase difference isessentially zero. This renders the frequency of the transmission pulseequal to the frequency of the receiving pulse.

Another advantageous configuration of the invention is that n localtransmission pulse signals with a mutual phase difference of 360/n° areprovided and that the local transmission pulse signal with the smallestphase difference relative to the receiving pulse signal is selected. Bypulse switching at the end of a data packet a transmission pulse isavailable, from which line control signals may be derived that aresynchronous with the receiving pulse of the preceding data packet. Suchsynchronous line control signals are included in drafts for an extensionof the IEEE 802.3 standard, concerned with the use of opticaltransmission paths.

According to another embodiment of the invention, a line control signalto be transmitted after the digital data signals is derived from thetransmission pulse signals selected from the n local transmissionpulses.

An embodiment is advantageous, in which the transmission pulse signal isderived from the receiving pulse signal, if the phase differencedeclines below a given threshold value.

According to a highly advantaqeous configuration of the invention thephase of the local transmission pulse signal is voltage controlled as afunction of the phase difference.

It is advantageous in this context to use an instantaneous value of thephase difference as the set value for the voltage controlled regulationof the phase of the local transmission pulse signal. The instantaneousphase difference between the receiving and the transmission signal ismaintained constant by a phase control circuit, which leads to an exactequalization of frequencies of the receiving and transmission pulses.

From the voltage controlled transmission pulse signal preferably a linecontrol signal to be transmitted after the digital signal is derived.The advantage here is that the frequency of the transmission pulsesignal varies continuously and not abruptly within the admissibletolerance range.

Of particular advantage is an embodiment in which the receiving pulsesignal is delayed by a period of time which is larger than or equal to aperiod of time corresponding to the number of bits intermediatelystored. It is assured in this manner that the buffer memory at the endof a data packet is completely read out. Instead of an independent timedelay, it is advantageous to carry out the delay in connection with thepulse derivation.

Relative to the present invention, it is advantageous to carry out thedecoding of the data of the receiving signal and the coding of the dataread out from the buffer memory.

The coding preferably is such that pulse derivation is possible.

In case of an existing preamble, the length losses caused by the pulsederivation are equalized.

According to a further development of the invention, a syntheticpreamble is essentially transmitted immediately following therecognition of an incoming data packet and prior to the conclusion ofthe pulse derivation from the incoming data signal. It is assured inthis manner that the preamble transmitted of a data packet is notshorter that the preamble received.

The receiving pulse signal is derived preferably by means of a phasecontrol circuit.

The present invention may be used advantageously in particular in aCSMA/CD access process according to IEEE 802.3.

The object of the invention may also be attained by a repeater of theaforementioned type, wherein a phase comparator is provided to determinethe phase difference between the receiving pulse signal and the localtransmission pulse signal.

If the phase difference declines below a given threshold value or if thephase difference preferably is zero, the receiving timing signal is usedas the transmitting timing signal.

If the phase difference declines below a given threshold value or if thephase difference preferably is zero, a timing signal switch transmitsthe receiving timing signal as the transmitting timing signal, thereceiving timing signal is used as the transmitting timing signal. Asthe result, the frequency of the transmitting timing signal is equal tothe frequence of the receiving timing signal. The maximum packet lengthmay therefore be of arbitrary length, without thereby endangering theoperation of the repeater. It is possible to carry out the intermediateamplification even if the frequency of the receiving timing signal isfar outside the tolerance band. The number of the bits to be storedintermediately thus depends only on the configuration of the buffermemory so that is possible to store a maximum of only 2 bits. In thismanner, both the startup time delay and the shortening of the interframe gap may be minimized.

In advantageous embodiment of the invention the local transmissiontiming signal generator is a voltage controlled oscillator. A scanningand holding element is provided in connection with the voltagecontrolled oscillator to store an instantaneous value of the phasecomparator output signal.

The voltage controlled oscillator preferably is a quartz stabilizedoscillator. Advantageously, the buffer memory is a asynchronousfirst-in-first-out (FIFO) buffer memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic view of a conventional CSMA/CD computernetwork.

FIGS. 2(a)-2(c) show signal variations in a schematic view todemonstrate phase jitter.

FIG. 3 shows the basic structure of a conventional circuit layout fortiming signal generation in a repeater.

FIGS. 4(a) and 4(b) shows schematic spatial views of data packets todemonstrate alterations applied to the data packet by the repeater shownin FIG. 3.

FIG. 5 shows a conventional pulse regeneration circuit broadenedrelative to the circuit layout shown in FIG. 3.

FIGS. 6(a) and 6(b) shows schematic perspective views of data packets toexplain the changes applied to the data packet by the repeater shown inFIG. 5.

FIG. 7 shows embodiment of the repeater according to the invention.

FIG. 8 shows another repeater embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 7 shows an embodiment of a pulse regeneration circuit for arepeater according to the invention. Parts of the circuit whichcorrespond to those of FIG. 5 are provided with the same symbols and arenot further described.

The receiving timing signal on the line 35 is conducted over a line 63to a phase comparator 64, a pulse delay stage 65 and a pulse selectionstage 66, for which control signals are further made available over aline 67. A timing signal generator 68 has n outlets 69-1, 69-2 . . .69-n, at which timing signals are provided, which relative to each otherhave a phase difference of 360/n degrees. These n timing signals aremade available to the pulse selection stage 66. The output signals ofthe pulse selection stage 66 arrive over a line 70 at a timing signalswitch 71 and phase comparator 64. The phase comparator 64 prepares anoutput signal for the control circuit 37 over a line 72. An outlet ofthe control circuit 37 is connected further with an inlet of the timesignal switch 71. The pulse delay stage 65 supplies to the timing signalswitch 71 a delayed receiving timing signal switch 71 a delayedreceiving timing signal oer the line 74. The output signal of the timingsignal switch 71 arrives over a line 75 at the coder 39.

The phase comparator 64 determines the phase difference between thelocal timing signal provided by the timing signal selection stage 66 andthe receiving timing signal determined by the pulse derivation andcoding stage 32. If the phase difference declines below a giventhreshold value which may tend to zero, this is communicated to thecontrol circuit 37 over the line 72.

Following the end of a data packet the receiving timing signal--asdemonstrated relative to FIG. 3--is immediately deactivated. If n bitsare stored intermediately and if the transmission timing signal isderived directly from the receiving timing signal, the receiving timingsignal must be delayed by at least n bit times, in order to be able tocompletely read out at the end of a data packet the memory 34. This iseffected by the pulse delay stage 65. In principle, this task may alsobe performed directly by the pulse derivation and decoding stage 32, sothat then the pulse delay stage 65 may be eliminated.

As a function of the output signal appearing on line 73 of the controlcircuit 37, the timing signal switch 71 prepares either the local timingsignal or the delayed receiving timing signal, which arrives over theline 75 at the code 39.

The timing selection switch 66 passes as a function of the controlsignal provided by the control circuit 37 over the line 67 the signal ofthe n oscillator signals that offers the smallest phase differencerelative to the receiving timing signal to its outlet.

At the onset of the reception of a data packet the mode of operationcorresponds entirely to the pulse regeneration circuit shown in FIG. 5.At the beginning of the retransmission of the preamble received in themode already explained the phase difference between the receiving timingsignal at the inlet of the buffer memory 34 and the readout timingsignal at the outlet of the buffer memory 34, which corresponds to thetransmission timing signal, may be within 0 degree and 360 degree. Dueto the frequency difference between the receiving timing signal and thelocal pulse signal the phase difference in the course of the datareception may decrease to 0 degree or increase to 360 degree, so thatthe state variation of the two timing signals is synchronous. This isrecognized by the phase comparator 64 and communicated to the controlcircuit 37, which then causes the timing signal switch 71 to switch fromthe local pulse signal to the receiving timing signal. From this time onthe frequencies of the receiving and the readout or transmission timingsignals are identical. It is therefore no longer necessary tointermediately store bits to equalize frequency differences, as isrequired in the case of the conventional repeaters. The intermediatestorage of a least 3 bits, as described above in connection withconventional circuits, may thus be eliminated. The buffer memory 34therefore must equalize only the phase differences between the receivingand the readout or transmission timing signal, i.e., 1 bit.

At the end of the data packet the pulse selection stage 66 selects theone of the n output signals of the oscillator as the local timing signalthat has the smallest phase difference relative to the receiving timingsignal. Following the complete read-out of the buffer memory 54 thetiming signal switch 71 passes the local timing signal through itsoutlet. The phase shift created by the switching in the transmissiontiming signal depends on the number of outlets of the oscillator andtherefore may be kept in principle as low as desired. Due to the pulseswitch, a transmission timing signal is available at the end of the datapacket, from which line control signals may be derived; said signalsbeing synchronous with the receiving timing signal of the preceding datapacket. Such synchrounous line control signals are contained in draftsto expand the IEEE 802.3 standard, which are concerned with the use ofoptical transmission paths.

If no line control signals are transmitted, pulse selection may beomitted. In this case one oscillator output signal is sufficient.

The read-in or read out of data into or out of the data memory 34 takesplace during the transmission timing signal. If the receiving timingsignal and the transmission timing signal are in phase relative to eachother, the bit read in a pulse period earlier, may be read out with thepositive side of the transmission timing signal. This signifies that atleast one bit must be stored intermediately. In the general case, a bitis read out after more than bit period. By the gradual increase in thephase shift to 360°, this delay time may grow to a maximum of two bitperiods. This means that that at least one bit must be storedintermediately. In the general case, a bit is read out after more thanbit period. By the gradual increase in the phase shift to 360°, thisdelay time may grow to a maximum of two bit periods. This means thataximum of two bits must be stored intermediately.

FIG. 8 shows another advantageous embodiment of the invention. Parts ofthe circuit of FIG. 8 corresponding to those of circuits alreadydiscussed, are provided with the same reference symbols and are notexplained again.

The phase detector 64 receives over the line 63 the receiving timingsignal standing at the line 35 and over a line 81 the output signal of avoltage controlled oscillator 82 The output signal of the phasecomparator 64 arrives over a line 83 at the inlet of a scanning andholding element 84 and over a line 85 to the actual value inlet of acontroller 86. The set value inlet of the controller 86 is connected bya line 87 with the outlet of a switch 88, which may be switched from aswitching position I into a switching position II and vice versa, byswitching signal provided by the control circuit in the line 89. Theconnector for the switching position I is connected with the outlet ofthe scanning and holding element 84 by a line 90, and the connector forthe switching position II with the inlet of the scanning and holdingelement 84 by a line 91, with the output signal of the phase comparator64 also being applied to said inlet 84. Another inlet of the scanningand holding element 84 is connected by means of a line 92 with thecontrol circuit 37.

The controller 86 emits an output signal over the line 93 to the voltagecontrolled oscillator 82, the output signal of which is provided notonly for the phase comparator 84 over the line 81, but also the coder 39over the line 94.

The phase comparator 64 provides the controller 86 and the inlet of thescanning and holding element 84 with a signal corresponding to the phasedifference between the transmission and reciving timing signal. As afunction of a control signal of the control circuit, the scanning andholding element stores an instantaneous value of the output signal ofthe phase comparator 64 and makes it available at its outlet, which isconnected by the line 90 with the connector of the switching position Iof the switch 88. The switch 88 passes through its outlet as a functionof the switching signal provided by the control circuit 37 over the line89 either the output signal of the phase comparator 64 or the value ofthe output signal of the phase comparator 64 instantaneously stored bythe scanning and holding element 84, which then forms the set value ofthe controller 86. The controller 86 provides the voltage controlledoscillator 82 with an output signal that is proportional to thedifference of its two input signals.

The voltage controlled oscillator delivers a signal the frequencywhereof depends on the output signal of the controller. It is asssumedin the process that its median frequency is within the tolerance zonerequired, which according to IEEE 802.3 amounts to ±1 kHz. Thistolerance requirement may be obtained with quartz stabilized, voltagecontrolled oscillators, the so-called VCXO. In this manner a phasecontrol circuit is established, the output frequencey of which is eitherequal to the median frequency of the VCXO--switch position II--or to thefrequency of the receiving timing signal--switch position I--, with thephase difference between the transmission and receiving timing signalsbeing determined by the output signal of the scanning and holdingelement 84.

In the rest state, i.e. when no data packet is being received, theswitch 88 is in position II; the control difference at the inlet of thecontroller 86 is zero. The VCXO therefore oscillates at its medianfrequency.

At the onset of the reception of a data packet the mode of operationcorresponds to that of the pulse regeneration circuit according to FIG.7. For a sufficiently long period of time following the end of thesynchronizing process of the pulse derivation, the duration whereofdepends on the dynamic properties of the phase comparator 64, theinstantaneous value of the output signal of the phase comparator 64 isstored and the switch 88 switched to position I. The instantaneous phasedifference between the transmission and receiving timing signals is thenmaintained constant by the phase control circuit. Consequently, thisleads to an exact equalization of the transmission and receiving timingsignals.

At the end of a data packet the switch is returned to position II,whereupon the frequency of the VCO again becomes the median frequency.

Corresponding to the discussion set forth relative to FIG. 7 of theemission of line control signals, in the embodiment shown in FIG. 8,line control signals may again be derived from the transmission timingsignal following the end of a data packet. The line control signals aresynchronous with the receiving timing signal of the preceding datapacket. Compared to the example of FIG. 7, the circuit layout accordingto FIG. 8 has the additional advantage that the frequency of thetransmission timing signal varies continously and not abruptly withinthe permissible tolerance range.

The present invention has been described by reference to examples. Thoseskilled in the art will find variations and modifications possiblewithout exceeding the scope of the inventive concept. For example, thebuffer memory 34 preferably is an asynchronous first in-first-out (FIFO)buffer memory. While the measures and characteristics of the inventionmay be applied in connection with all repeaters for digital transmissionsystems, the present invention is especially advantageous with theCSMA/CD access process according to the IEEE Standard 802.3.

We claim:
 1. A process for intermediate amplification of digital signalstransmitted as data packets, with amplitude and pulse regeneration,wherein pulse regeneration comprises the steps of:derivation of areceiving timing signal from a signal received; reading in bits of thesignal received with the receiving timing signal into a buffer memory;and reading out the bits from buffer memory in accordance with a localtransmission timing signal, altering the phase of said localtransmission timing signal as a function of a phase difference betweensaid receiving timing signal and said local transmission timing signal;recognizing an incoming data packet; transmitting a synthetic preambleessentially immediately following recognition of an incoming data packetand prior to completion of said step of derivation of a receiving timingsignal.
 2. A process according to claim 1, wherein said localtransmission timing signal phase is altered so that said receivingtiming signal and said local transmission timing signal are essentiallyin agreement.
 3. A process according to claim 2, further comprising thestep of using a voltage level to control said local transmission timingsignal phase as a function of phase difference.
 4. A process accordingto claim 2, wherein said step of reading out the bits from said buffermemory is switched to be in accordance with said receiving timing signalas soon as the phase difference between said receiving timing signal andsaid local timing signal has become essentially zero.
 5. A processaccording to claim 4, further comprising the step of generating aplurality of n timing signals exhibiting a phase different of 360°/nrelative to each other selecting one of said n timing signals with thesmallest phase difference relative to said receiving timing signal assaid local transmission timing signal.
 6. A process according to claim4, further comprising the step of deriving a line control signal, to betransmitted after the digital data signals, from said selected localtransmission timing signal.
 7. A process according to claim 4, furthercomprising the step of using a voltage level to control said localtransmission timing signal phase as a function of phase difference.
 8. Aprocess according to claim 1, wherein said local transmission timingsignal is derived from said receiving timing signal, if said phasedifference is below a predetermined threshold value.
 9. A processaccording to claim 1, further comprising the step of utilizing a voltagelevel to control said local transmission timing signal phase as afunction of said phase difference.
 10. A process according to claim 9,wherein an instantaneous value of the phase difference is used as a setvalue for the voltage level control of said local transmission timingsignal phase.
 11. A process according to claim 9, further comprising thestep of deriving a line control signal from the voltage controlled localtransmission timing signal.
 12. A process according to claim 1, furthercomprising the step of delaying said receiving timing signal by a periodof time, which is longer than or equal to a period of time correspondingto a number of bits intermediately stored in said buffer memory.
 13. Aprocess according to claim 12, wherein said delay is effected inconnection with said step of derivation of said receiving timing signal.14. A process according to claim 1 further comprising the steps ofdecoding data of said receiving signal and coding data read out from abuffer memory.
 15. A process according to claim 13, wherein said step ofcoding is reversible.
 16. A process according to claim 1, furthercomprising the step of equalizing losses of signal length due to thepulse derivation when a signal preamble is present.
 17. A processaccording to claim 1 wherein said step of derivation of said receivingtiming signal is effected by a phase control circuit.
 18. A processaccording to claim 1 wherein said process is used in connection with aCSMA/CD access process according to IEEE standard 802.3.
 19. A digitalsignal repeater comprising:an amplitude and pulse regeneration circuitfor data packets, wherein said regeneration circuit includes a receivingtiming signal deriver, a buffer memory connected to said receivingtiming signal deriver, a control circuit connected to said buffer memoryand said receiving timing signal deriver, a local transmission timingsignal generator, a phase comparator connected to said receiving timingsignal deriver and said local transmission timing signal generator, anda synthetic preamble generator responsive to said control circuit.
 20. Arepeated according to claim 19, further comprising a timing signalswitch connected to said receiving timing signal deriver and said localtransmission timing signal generator, wherein said timing signal switchis responsive to said phase comparator and configured to pass areceiving timing signal as a transmission timing signal, when a phasedifference, between said receiving timing signal and a localtransmission timing signal from said local transmission timing generatordeclines under a predetermined threshold value.
 21. A repeater accordingto claim 19, wherein said local transmission timing signal generatorexhibits a plurality of n timing signals each having a phase differenceof 360°/n relative to each other.
 22. A repeater according to claim 21,further comprising a transmission timing signal selection stage,responsive to said n timing signals and said receiving timing signal,configured to select one of said n signals with the smallest phasedifference relative to said receiving timing signal.
 23. A repeateraccording to claim 19, wherein said local transmission timing signalgenerator is a voltage controlled oscillator.
 24. A repeater accordingto claim 23, further comprising a scanning and holding element connectedto said phase comparator.
 25. A repeater according to claim 23 whereinsaid voltage controlled oscillator is a quartz stabilized, voltagecontrolled oscillator.
 26. A repeater according to claim 19 wherein saidbuffer memory is an asynchronous first-in-first-out buffer memory.
 27. Arepeater according to claim 24 wherein said scanning and holding elementis configured to store an instantaneous value output signal of saidphase comparator.
 28. A repeater according to claim 19 wherein saidphase comparator is configured to determine phase difference.